1. Field of the Invention
This invention relates to the field of integrated circuit fabrication, and in particularly to a method of making high-voltage bipolar/CMOS/DMOS (BCD) devices.
2. Description of Related Art
Bipolar/CMOS/DMOS (BCD) devices are employed in high voltage applications. They typically use a Silicon On Insulator (SOI) substrate or a complex epitaxial substrate combining at least two layers of two different types of dopant, N-Type and P-Type and a very complex sequence of masks to produce the required transistors and other active components. They only provide a partial combination of standard and high-voltage transistors for the designers, require process modifications, which can be major, to fulfill various voltage operation ranges.
The following three references describe Bipolar/CMOS/DMOS (BCD) processes which require the use of a substrate combining two or more layers of different dopant types which may or may not be buried under the silicon surface: C. Contiero, P. Galbiati, M. Palmieri, L. Vecchi, “LDMOS Implemetation by Large Tilt Implant in 0.6 μm BCD5 Process, Flash Memory Compatible”, International Symposium on Power Semiconductor Devices and ICs (ISPSD), 1996, pp. 75-78; U.S. Pat. No. 6,111,297 “MOS-technology power device integrated structure . . . ”; and U.S. Pat. No. 4,795,716 “Method of making a power IC structure with enhancement . . . ”
This BCD approach requies extra masks and processing steps for lateral isolation as well as an expensive epitaxial deposition reactor used to generate buried epitaxial layers. A major disadvantage of this approach resides in the fact that the resulting DMOS transistors are mostly vertical.
The following five references describe other Bipolar/CMOS/DMOS (BCD) processes which require the use of a Silicon-On-Insulator (SOI) substrate to integrate the high-voltage components on a oxide dielectric layer buried under the silicon surface: J. A. van der Pol, “A-BCD: An Economic 100V RESURF Silicon-On-Insulator BCD Technology for Consumer and Automotive Applications”, International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2000, pp. 327-330; U.S. Pat. No. 6,130,458 “Power IC having SOI structure”; U.S. Pat. No. 5,939,755 “Power IC having high-side and low-side switches in an SOI . . . ”; U.S. Pat. No. 5,854,113 “Method for fabricating power transistor using . . . ”; U.S. Pat. No. 5,681,761 “Microwave power SOI-MOSFET with high conductivity . . . ”; and U.S. Pat. No. 5,578,506 “Method of fabricating improved lateral Silicon-On-Insulator . . . ”
These BCD processes on SOI wafers using very expensive SOI substrates also add costs and additional processing steps for lateral isolation. More importantly, the high-voltage components built on SOI substrates cannot be integrated on the bulk or epitaxial wafer of our invention because some components would not be self-isolated from other components and would share common drain electrodes.
These and other Prior Art BCD processes that can be found in the literature cannot integrate high-voltage single extended NMOSFET or high-voltage double extended NMOSFET distinct from the DMOS transistor simply because these processes do not provide an isolated N-Well in a P-Type region, thus forming the required isolating junction. The resulting number of high-voltage N-Channel components is therefore reduced compared to our proposed invention.